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<title>Field-programmable gate array</title>

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<span id="openzim-page-title" class="mw-page-title-main"><span class="mw-page-title-main">Field-programmable gate array</span></span>

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</style><div role="note" class="hatnote navigation-not-searchable">"FPGA" redirects here; not to be confused with <a href="Flip-chip_pin_grid_array" class="mw-redirect" title="Flip-chip pin grid array">Flip-chip pin grid array</a>.</div>

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</style><div class="thumb tmulti tright"><div class="thumbinner multiimageinner" style="width:408px;max-width:408px"><div class="trow"><div class="theader">Spartan FPGA from <a href="Xilinx" title="Xilinx">Xilinx</a></div></div><div class="trow"><div class="tsingle" style="width:202px;max-width:202px"><div class="thumbimage"><span typeof="mw:File"></span></div><div class="thumbcaption"><a href="Integrated_circuit_packaging" title="Integrated circuit packaging">Package</a></div></div><div class="tsingle" style="width:202px;max-width:202px"><div class="thumbimage"><span typeof="mw:File"></span></div><div class="thumbcaption"><a href="Die_(integrated_circuit)" title="Die (integrated circuit)">Die</a></div></div></div></div></div>

<p>A <b>field-programmable gate array</b> (<b>FPGA</b>) is a type of configurable <a href="Integrated_circuit" title="Integrated circuit">integrated circuit</a> that can be repeatedly programmed after manufacturing. FPGAs are a subset of logic devices referred to as <a href="Programmable_logic_devices" class="mw-redirect" title="Programmable logic devices">programmable logic devices</a> (PLDs). They consist of a grid-connected array of <a href="Programmable_logic_device" title="Programmable logic device">programmable</a> <a href="Logic_block" title="Logic block">logic blocks</a> that can be configured "in the field" to interconnect with other logic blocks to perform various digital functions. FPGAs are often used in limited (low) quantity production of custom-made products, and in research and development, where the higher cost of individual FPGAs is not as important and where creating and manufacturing a custom circuit would not be feasible. Other applications for FPGAs include the telecommunications, automotive, aerospace, and industrial sectors, which benefit from their flexibility, high signal processing speed, and parallel processing abilities.

</p><p>A FPGA configuration is generally written using a <a href="Hardware_description_language" title="Hardware description language">hardware description language</a> (HDL) e.g. <a href="VHDL" title="VHDL">VHDL</a>, similar to the ones used for <a href="Application-specific_integrated_circuit" title="Application-specific integrated circuit">application-specific integrated circuits</a> (ASICs). <a href="Circuit_diagram" title="Circuit diagram">Circuit diagrams</a> were formerly used to write the configuration.

</p><p>The logic blocks of an FPGA can be configured to perform complex <a href="Combinational_logic" title="Combinational logic">combinational functions</a>, or act as simple <a href="Logic_gate" title="Logic gate">logic gates</a> like <a href="AND_gate" title="AND gate">AND</a> and <a href="XOR_gate" title="XOR gate">XOR</a>. In most FPGAs, logic blocks also include <a href="Memory_cell_(computing)" title="Memory cell (computing)">memory elements</a>, which may be simple <a href="Flip-flop_(electronics)" title="Flip-flop (electronics)">flip-flops</a> or more sophisticated blocks of memory.<sup id="cite_ref-FPGA_1-0" class="reference"><a href="#cite_note-FPGA-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup> Many FPGAs can be reprogrammed to implement different <a href="Boolean_function" title="Boolean function">logic functions</a>, allowing flexible <a href="Reconfigurable_computing" title="Reconfigurable computing">reconfigurable computing</a> as performed in <a href="Computer_software" class="mw-redirect" title="Computer software">computer software</a>.

</p><p>FPGAs also have a role in <a href="Embedded_system" title="Embedded system">embedded system</a> development due to their capability to start system software development simultaneously with hardware, enable system performance simulations at a very early phase of the development, and allow various system trials and design iterations before finalizing the system architecture.<sup id="cite_ref-2" class="reference"><a href="#cite_note-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup>

</p><p>FPGAs are also commonly used during the development of ASICs to speed up the simulation process.

</p>

<div class="mw-heading mw-heading2"><h2 id="History">History</h2></div>

<p>The FPGA industry sprouted from <a href="Programmable_read-only_memory" class="mw-redirect" title="Programmable read-only memory">programmable read-only memory</a> (PROM) and <a href="Programmable_logic_device" title="Programmable logic device">programmable logic devices</a> (PLDs). PROMs and PLDs both had the option of being programmed in batches in a factory or in the field (field-programmable).<sup id="cite_ref-history_3-0" class="reference"><a href="#cite_note-history-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup>

</p><p><a href="Altera" title="Altera">Altera</a> was founded in 1983 and delivered the industry's first reprogrammable logic device in 1984 – the EP300 – which featured a quartz window in the package that allowed users to shine an ultra-violet lamp on the <a href="Die_(integrated_circuit)" title="Die (integrated circuit)">die</a> to erase the <a href="EPROM" title="EPROM">EPROM</a> cells that held the device configuration.<sup id="cite_ref-4" class="reference"><a href="#cite_note-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup>

</p><p><a href="Xilinx" title="Xilinx">Xilinx</a> produced the first commercially viable field-programmable <a href="Gate_array" title="Gate array">gate array</a> in 1985<sup id="cite_ref-history_3-1" class="reference"><a href="#cite_note-history-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup> – the XC2064.<sup id="cite_ref-:0_5-0" class="reference"><a href="#cite_note-:0-5"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup> The XC2064 had programmable gates and programmable interconnects between gates, the beginnings of a new technology and market.<sup id="cite_ref-four_6-0" class="reference"><a href="#cite_note-four-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup> The XC2064 had 64 configurable logic blocks (CLBs), with two three-input <a href="Lookup_table" title="Lookup table">lookup tables</a> (LUTs).<sup id="cite_ref-clive_7-0" class="reference"><a href="#cite_note-clive-7"><span class="cite-bracket">[</span>7<span class="cite-bracket">]</span></a></sup>

</p><p>In 1987, the <a href="Naval_Surface_Warfare_Center" title="Naval Surface Warfare Center">Naval Surface Warfare Center</a> funded an experiment proposed by Steve Casselman to develop a computer that would implement 600,000 reprogrammable gates. Casselman was successful and a patent related to the system was issued in 1992.<sup id="cite_ref-history_3-2" class="reference"><a href="#cite_note-history-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup>

</p><p>Altera and Xilinx continued unchallenged and quickly grew from 1985 to the mid-1990s when competitors sprouted up, eroding a significant portion of their market share. By 1993, Actel (later <a href="Microsemi" title="Microsemi">Microsemi</a>, now <a href="Microchip_Technology" title="Microchip Technology">Microchip</a>) was serving about 18 percent of the market.<sup id="cite_ref-four_6-1" class="reference"><a href="#cite_note-four-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup>

</p><p>The 1990s were a period of rapid growth for FPGAs, both in circuit sophistication and the volume of production. In the early 1990s, FPGAs were primarily used in <a href="Telecommunications" title="Telecommunications">telecommunications</a> and <a href="Computer_network" title="Computer network">networking</a>. By the end of the decade, FPGAs found their way into consumer, automotive, and industrial applications.<sup id="cite_ref-Maxfield_8-0" class="reference"><a href="#cite_note-Maxfield-8"><span class="cite-bracket">[</span>8<span class="cite-bracket">]</span></a></sup>

</p><p>By 2013, Altera (31 percent), Xilinx (36 percent) and Actel (10 percent) together represented approximately 77 percent of the FPGA market.<sup id="cite_ref-9" class="reference"><a href="#cite_note-9"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup>

</p><p>Companies like Microsoft have started to use FPGAs to accelerate high-performance, computationally intensive systems (like the <a href="Data_center" title="Data center">data centers</a> that operate their <a href="Bing_search_engine" class="mw-redirect" title="Bing search engine">Bing search engine</a>), due to the <a href="Performance_per_watt" title="Performance per watt">performance per watt</a> advantage FPGAs deliver.<sup id="cite_ref-10" class="reference"><a href="#cite_note-10"><span class="cite-bracket">[</span>10<span class="cite-bracket">]</span></a></sup> Microsoft began using FPGAs to <a href="Hardware_acceleration" title="Hardware acceleration">accelerate</a> Bing in 2014, and in 2018 began deploying FPGAs across other data center workloads for their <a href="Microsoft_Azure" title="Microsoft Azure">Azure</a> <a href="Cloud_computing" title="Cloud computing">cloud computing</a> platform.<sup id="cite_ref-ProjCatapult_11-0" class="reference"><a href="#cite_note-ProjCatapult-11"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup>

</p><p>Since 2019, modern generation of FPGAs have been integrated with other architectures like <a href="AI_engine" title="AI engine">AI engines</a> to target workloads in artificial intelligence domain.<sup id="cite_ref-12" class="reference"><a href="#cite_note-12"><span class="cite-bracket">[</span>12<span class="cite-bracket">]</span></a></sup>

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<div class="mw-heading mw-heading3"><h3 id="Growth">Growth</h3></div>

<p>The following timelines indicate progress in different aspects of FPGA design.

</p>

<div class="mw-heading mw-heading4"><h4 id="Gates">Gates</h4></div>

<ul><li>1987: 9,000 gates, Xilinx<sup id="cite_ref-four_6-2" class="reference"><a href="#cite_note-four-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup></li>

<li>1992: 600,000, Naval Surface Warfare Department<sup id="cite_ref-history_3-3" class="reference"><a href="#cite_note-history-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup></li>

<li>Early 2000s: millions<sup id="cite_ref-Maxfield_8-1" class="reference"><a href="#cite_note-Maxfield-8"><span class="cite-bracket">[</span>8<span class="cite-bracket">]</span></a></sup></li>

<li>2013: 50 million, Xilinx<sup id="cite_ref-gates2013_13-0" class="reference"><a href="#cite_note-gates2013-13"><span class="cite-bracket">[</span>13<span class="cite-bracket">]</span></a></sup></li></ul>

<div class="mw-heading mw-heading4"><h4 id="Market_size">Market size</h4></div>

<ul><li>1985: First commercial FPGA : Xilinx XC2064<sup id="cite_ref-:0_5-1" class="reference"><a href="#cite_note-:0-5"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-four_6-3" class="reference"><a href="#cite_note-four-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup></li>

<li>1987: $14 million<sup id="cite_ref-four_6-4" class="reference"><a href="#cite_note-four-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup></li>

<li><abbr title="circa">c.</abbr><span style="white-space:nowrap;"> 1993</span>: >$385 million<sup id="cite_ref-four_6-5" class="reference"><a href="#cite_note-four-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup></li>

<li>2005: $1.9 billion<sup id="cite_ref-instat_14-0" class="reference"><a href="#cite_note-instat-14"><span class="cite-bracket">[</span>14<span class="cite-bracket">]</span></a></sup></li>

<li>2010 estimates: $2.75 billion<sup id="cite_ref-instat_14-1" class="reference"><a href="#cite_note-instat-14"><span class="cite-bracket">[</span>14<span class="cite-bracket">]</span></a></sup></li>

<li>2013: $5.4 billion<sup id="cite_ref-grandviewresearch.com_15-0" class="reference"><a href="#cite_note-grandviewresearch.com-15"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup></li>

<li>2020 estimate: $9.8 billion<sup id="cite_ref-grandviewresearch.com_15-1" class="reference"><a href="#cite_note-grandviewresearch.com-15"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup></li>

<li>2030 estimate: $23.34 billion<sup id="cite_ref-16" class="reference"><a href="#cite_note-16"><span class="cite-bracket">[</span>16<span class="cite-bracket">]</span></a></sup></li></ul>

<div class="mw-heading mw-heading4"><h4 id="Design_starts">Design starts</h4></div>

<p>A <i>design start</i> is a new custom design for implementation on an FPGA.

</p>

<div class="mw-heading mw-heading2"><h2 id="Design">Design</h2></div>

<p>Contemporary FPGAs have ample <a href="Logic_gate" title="Logic gate">logic gates</a> and RAM blocks to implement complex digital computations. FPGAs can be used to implement any logical function that an <a href="ASIC" class="mw-redirect" title="ASIC">ASIC</a> can perform. The ability to update the functionality after shipping, <a href="Partial_re-configuration" class="mw-redirect" title="Partial re-configuration">partial re-configuration</a> of a portion of the design<sup id="cite_ref-19" class="reference"><a href="#cite_note-19"><span class="cite-bracket">[</span>19<span class="cite-bracket">]</span></a></sup> and the low non-recurring engineering costs relative to an ASIC design (notwithstanding the generally higher unit cost), offer advantages for many applications.<sup id="cite_ref-FPGA_1-1" class="reference"><a href="#cite_note-FPGA-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup>

</p><p>As FPGA designs employ very fast I/O rates and bidirectional data <a href="Bus_(computing)" title="Bus (computing)">buses</a>, it becomes a challenge to verify correct timing of valid data within setup time and hold time.<sup id="cite_ref-20" class="reference"><a href="#cite_note-20"><span class="cite-bracket">[</span>20<span class="cite-bracket">]</span></a></sup> <a href="Floorplan_(microelectronics)" title="Floorplan (microelectronics)">Floor planning</a> helps resource allocation within FPGAs to meet these timing constraints.

</p><p>Some FPGAs have analog features in addition to digital functions. The most common analog feature is a programmable <a href="Slew_rate" title="Slew rate">slew rate</a> on each output pin. This allows the user to set low rates on lightly loaded pins that would otherwise <a href="Electrical_resonance" title="Electrical resonance">ring</a> or <a href="Coupling_(electronics)" title="Coupling (electronics)">couple</a> unacceptably, and to set higher rates on heavily loaded high-speed channels that would otherwise run too slowly.<sup id="cite_ref-21" class="reference"><a href="#cite_note-21"><span class="cite-bracket">[</span>21<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-22" class="reference"><a href="#cite_note-22"><span class="cite-bracket">[</span>22<span class="cite-bracket">]</span></a></sup> Also common are quartz-<a href="Crystal_oscillator" title="Crystal oscillator">crystal oscillator</a> driver circuitry, on-chip <a href="RC_oscillator" title="RC oscillator">RC oscillators</a>, and <a href="Phase-locked_loop" title="Phase-locked loop">phase-locked loops</a> with embedded <a href="Voltage-controlled_oscillator" title="Voltage-controlled oscillator">voltage-controlled oscillators</a> used for clock generation and management as well as for high-speed serializer-deserializer (SERDES) transmit clocks and receiver clock recovery. Fairly common are differential <a href="Comparator" title="Comparator">comparators</a> on input pins designed to be connected to <a href="Differential_signaling" class="mw-redirect" title="Differential signaling">differential signaling</a> channels. A few <a href="Mixed_signal" class="mw-redirect" title="Mixed signal">mixed signal</a> FPGAs have integrated peripheral <a href="Analog-to-digital_converter" title="Analog-to-digital converter">analog-to-digital converters</a> (ADCs) and <a href="Digital-to-analog_converter" title="Digital-to-analog converter">digital-to-analog converters</a> (DACs) with analog signal conditioning blocks, allowing them to operate as a <a href="System_on_a_chip" title="System on a chip">system on a chip</a> (SoC).<sup id="cite_ref-23" class="reference"><a href="#cite_note-23"><span class="cite-bracket">[</span>23<span class="cite-bracket">]</span></a></sup> Such devices blur the line between an FPGA, which carries digital ones and zeros on its internal programmable interconnect fabric, and <a href="Field-programmable_analog_array" title="Field-programmable analog array">field-programmable analog array</a> (FPAA), which carries analog values on its internal programmable interconnect fabric.

</p>

<div class="mw-heading mw-heading3"><h3 id="Logic_blocks">Logic blocks</h3></div>

<div role="note" class="hatnote navigation-not-searchable">Main article: <a href="Logic_block" title="Logic block">Logic block</a></div>

<p>The most common FPGA architecture consists of an array of <a href="Logic_block" title="Logic block">logic blocks</a> called configurable logic blocks (CLBs) or logic array blocks (LABs) (depending on vendor), <a href="I/O_address" class="mw-redirect" title="I/O address">I/O pads</a>, and routing channels.<sup id="cite_ref-FPGA_1-2" class="reference"><a href="#cite_note-FPGA-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup> Generally, all the routing channels have the same width (number of signals). Multiple I/O pads may fit into the height of one row or the width of one column in the array.

</p><p>"An application circuit must be mapped into an FPGA with adequate resources. While the number of logic blocks and I/Os required is easily determined from the design, the number of routing channels needed may vary considerably even among designs with the same amount of logic. For example, a <a href="Crossbar_switch" title="Crossbar switch">crossbar switch</a> requires much more routing than a <a href="Systolic_array" title="Systolic array">systolic array</a> with the same gate count. Since unused routing channels increase the cost (and decrease the performance) of the FPGA without providing any benefit, FPGA manufacturers try to provide just enough channels so that most designs that will fit in terms of <a href="Lookup_table#Hardware_LUTs" title="Lookup table">lookup tables</a> (LUTs) and I/Os can be <a href="Routing_(electronic_design_automation)" title="Routing (electronic design automation)">routed</a>. This is determined by estimates such as those derived from <a href="Rent's_rule" title="Rent's rule">Rent's rule</a> or by experiments with existing designs."<sup id="cite_ref-24" class="reference"><a href="#cite_note-24"><span class="cite-bracket">[</span>24<span class="cite-bracket">]</span></a></sup>

</p><p>In general, a logic block consists of a few logical cells. A typical cell consists of a 4-input LUT, a <a href="Adder_(electronics)" title="Adder (electronics)">full adder</a> (FA) and a <a href="D-type_flip-flop" class="mw-redirect" title="D-type flip-flop">D-type flip-flop</a>. The LUT might be split into two 3-input LUTs. In <i>normal mode</i> those are combined into a 4-input LUT through the first <a href="Multiplexer" title="Multiplexer">multiplexer</a> (mux). In <i>arithmetic</i> mode, their outputs are fed to the adder. The selection of mode is programmed into the second mux. The output can be either <a href="Synchronous_circuit" title="Synchronous circuit">synchronous</a> or <a href="Asynchronous_circuit" title="Asynchronous circuit">asynchronous</a>, depending on the programming of the third mux. In practice, the entire adder or parts of it are <a href="Shannon_expansion" class="mw-redirect" title="Shannon expansion">stored as functions</a> into the LUTs in order to save <a href="Circuit_utilization" class="mw-redirect" title="Circuit utilization">space</a>.<sup id="cite_ref-25" class="reference"><a href="#cite_note-25"><span class="cite-bracket">[</span>25<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-26" class="reference"><a href="#cite_note-26"><span class="cite-bracket">[</span>26<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-27" class="reference"><a href="#cite_note-27"><span class="cite-bracket">[</span>27<span class="cite-bracket">]</span></a></sup>

</p>

<div class="mw-heading mw-heading3"><h3 id="Hard_blocks">Hard blocks</h3></div>

<p>Modern FPGA families expand upon the above capabilities to include higher-level functionality fixed in silicon. Having these common functions embedded in the circuit reduces the area required and gives those functions increased performance compared to building them from logical primitives. Examples of these include <a href="Binary_multiplier" title="Binary multiplier">multipliers</a>, generic <a href="Digital_signal_processor" title="Digital signal processor">DSP blocks</a>, <a href="Microprocessor" title="Microprocessor">embedded processors</a>, high-speed I/O logic and embedded <a href="Computer_memory" title="Computer memory">memories</a>.

</p><p>Higher-end FPGAs can contain high-speed <a href="Multi-gigabit_transceiver" title="Multi-gigabit transceiver">multi-gigabit transceivers</a> and <i>hard IP cores</i> such as <a href="Processor_core" class="mw-redirect" title="Processor core">processor cores</a>, <a href="Ethernet" title="Ethernet">Ethernet</a> <a href="Medium_access_control" title="Medium access control">medium access control units</a>, <a href="Conventional_PCI" class="mw-redirect" title="Conventional PCI">PCI</a> or <a href="PCI_Express" title="PCI Express">PCI Express</a> controllers, and external <a href="Memory_controller" title="Memory controller">memory controllers</a>. These cores exist alongside the programmable fabric, but they are built out of <a href="Transistor" title="Transistor">transistors</a> instead of LUTs so they have ASIC-level performance and power consumption without consuming a significant amount of fabric resources, leaving more of the fabric free for the application-specific logic. The multi-gigabit transceivers also contain high-performance <a href="Signal_conditioning" title="Signal conditioning">signal conditioning</a> circuitry along with high-speed serializers and deserializers, components that cannot be built out of LUTs. Higher-level physical layer (PHY) functionality such as <a href="Line_coding" class="mw-redirect" title="Line coding">line coding</a> may or may not be implemented alongside the serializers and deserializers in hard logic, depending on the FPGA.

</p>

<p>An alternate approach to using hard macro processors is to make use of <a href="Soft_processor" class="mw-redirect" title="Soft processor">soft processor</a> <a href="Semiconductor_intellectual_property_core" title="Semiconductor intellectual property core">IP cores</a> that are implemented within the FPGA logic. <a href="Nios_II" title="Nios II">Nios II</a>, <a href="MicroBlaze" title="MicroBlaze">MicroBlaze</a> and <a href="Mico32" class="mw-redirect" title="Mico32">Mico32</a> are examples of popular softcore processors. Many modern FPGAs are programmed at <i>run time</i>, which has led to the idea of <a href="Reconfigurable_computing" title="Reconfigurable computing">reconfigurable computing</a> or reconfigurable systems – <a href="CPU" class="mw-redirect" title="CPU">CPUs</a> that reconfigure themselves to suit the task at hand. Additionally, new non-FPGA architectures are beginning to emerge. Software-configurable microprocessors such as the Stretch S5000 adopt a hybrid approach by providing an array of processor cores and FPGA-like programmable cores on the same chip.

</p>

<div class="mw-heading mw-heading3"><h3 id="Integration">Integration</h3></div>

<p>In 2012 the coarse-grained architectural approach was taken a step further by combining the <a href="Logic_block" title="Logic block">logic blocks</a> and interconnects of traditional FPGAs with embedded <a href="Microprocessor" title="Microprocessor">microprocessors</a> and related peripherals to form a complete <a href="System_on_a_chip" title="System on a chip">system on a programmable chip</a>. Examples of such hybrid technologies can be found in the <a href="Xilinx" title="Xilinx">Xilinx</a> Zynq-7000 all <a href="Programmable_SoC" class="mw-redirect" title="Programmable SoC">programmable SoC</a>,<sup id="cite_ref-Xilinx-Inc-Oct-2011-8-K_28-0" class="reference"><a href="#cite_note-Xilinx-Inc-Oct-2011-8-K-28"><span class="cite-bracket">[</span>28<span class="cite-bracket">]</span></a></sup> which includes a 1.0 <a href="GHz" class="mw-redirect" title="GHz">GHz</a> dual-core <a href="ARM_Cortex-A9" title="ARM Cortex-A9">ARM Cortex-A9</a> MPCore processor <a href="Embedded_system" title="Embedded system">embedded</a> within the FPGA's logic fabric,<sup id="cite_ref-Xilinx-Inc-May-2011-10-K_29-0" class="reference"><a href="#cite_note-Xilinx-Inc-May-2011-10-K-29"><span class="cite-bracket">[</span>29<span class="cite-bracket">]</span></a></sup> or in the <a href="Altera" title="Altera">Altera</a> Arria V FPGA, which includes an 800 MHz <a href="Dual-core" class="mw-redirect" title="Dual-core">dual-core</a> <a href="ARM_Cortex-A9" title="ARM Cortex-A9">ARM Cortex-A9</a> MPCore. The <a href="Atmel" title="Atmel">Atmel</a> FPSLIC is another such device, which uses an <a href="Atmel_AVR" class="mw-redirect" title="Atmel AVR">AVR</a> processor in combination with Atmel's programmable logic architecture. The <a href="Microsemi" title="Microsemi">Microsemi</a> <a href="SmartFusion" class="mw-redirect" title="SmartFusion">SmartFusion</a> devices incorporate an ARM Cortex-M3 hard processor core (with up to 512 kB of <a href="Flash_memory" title="Flash memory">flash</a> and 64 kB of RAM) and analog <a href="Peripheral" title="Peripheral">peripherals</a> such as a multi-channel <a href="Analog-to-digital_converter" title="Analog-to-digital converter">analog-to-digital converters</a> and <a href="Digital-to-analog_converter" title="Digital-to-analog converter">digital-to-analog converters</a> in their <a href="Flash_memory" title="Flash memory">flash memory</a>-based FPGA fabric.

</p>

<div class="mw-heading mw-heading3"><h3 id="Clocking">Clocking</h3></div>

<p>Most of the logic inside of an FPGA is <a href="Synchronous_circuit" title="Synchronous circuit">synchronous circuitry</a> that requires a <a href="Clock_signal" title="Clock signal">clock signal</a>. FPGAs contain dedicated global and regional routing networks for clock and reset, typically implemented as an <a href="H_tree" title="H tree">H tree</a>, so they can be delivered with minimal <a href="Clock_skew" title="Clock skew">skew</a>. FPGAs may contain analog <a href="Phase-locked_loop" title="Phase-locked loop">phase-locked loop</a> or <a href="Delay-locked_loop" title="Delay-locked loop">delay-locked loop</a> components to synthesize new <a href="Clock_frequencies" class="mw-redirect" title="Clock frequencies">clock frequencies</a> and manage <a href="Jitter" title="Jitter">jitter</a>. Complex designs can use multiple clocks with different frequency and phase relationships, each forming separate <a href="Clock_domain" class="mw-redirect" title="Clock domain">clock domains</a>. These clock signals can be generated locally by an oscillator or they can be recovered from a <a href="Data_stream" title="Data stream">data stream</a>. Care must be taken when building <a href="Clock_domain_crossing" title="Clock domain crossing">clock domain crossing</a> circuitry to avoid <a href="Metastability_(electronics)" title="Metastability (electronics)">metastability</a>. Some FPGAs contain <a href="Dual_port_RAM" class="mw-redirect" title="Dual port RAM">dual port RAM</a> blocks that are capable of working with different clocks, aiding in the construction of building <a href="FIFO_(computing_and_electronics)" title="FIFO (computing and electronics)">FIFOs</a> and dual port buffers that bridge clock domains.

</p>

<div class="mw-heading mw-heading3"><h3 id="3D_architectures">3D architectures</h3></div>

<p>To shrink the size and power consumption of FPGAs, vendors such as <a href="Tabula_(company)" class="mw-redirect" title="Tabula (company)">Tabula</a> and <a href="Xilinx" title="Xilinx">Xilinx</a> have introduced <a href="Three-dimensional_integrated_circuit" title="Three-dimensional integrated circuit">3D or stacked architectures</a>.<sup id="cite_ref-30" class="reference"><a href="#cite_note-30"><span class="cite-bracket">[</span>30<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-lawrence_31-0" class="reference"><a href="#cite_note-lawrence-31"><span class="cite-bracket">[</span>31<span class="cite-bracket">]</span></a></sup> Following the introduction of its 28 nm 7-series FPGAs, Xilinx said that several of the highest-density parts in those FPGA product lines will be constructed using multiple dies in one package, employing technology developed for 3D construction and stacked-die assemblies.

</p><p>Xilinx's approach stacks several (three or four) active FPGA dies side by side on a silicon <a href="Interposer" title="Interposer">interposer</a> – a single piece of silicon that carries passive interconnect.<sup id="cite_ref-lawrence_31-1" class="reference"><a href="#cite_note-lawrence-31"><span class="cite-bracket">[</span>31<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-32" class="reference"><a href="#cite_note-32"><span class="cite-bracket">[</span>32<span class="cite-bracket">]</span></a></sup> The multi-die construction also allows different parts of the FPGA to be created with different process technologies, as the process requirements are different between the FPGA fabric itself and the very high speed 28 Gbit/s serial transceivers. An FPGA built in this way is called a <i><a href="Heterogeneous_computing" title="Heterogeneous computing">heterogeneous</a> FPGA</i>.<sup id="cite_ref-33" class="reference"><a href="#cite_note-33"><span class="cite-bracket">[</span>33<span class="cite-bracket">]</span></a></sup>

</p><p>Altera's heterogeneous approach involves using a single monolithic FPGA die and connecting other dies and technologies to the FPGA using Intel's embedded multi_die interconnect bridge (EMIB) technology.<sup id="cite_ref-34" class="reference"><a href="#cite_note-34"><span class="cite-bracket">[</span>34<span class="cite-bracket">]</span></a></sup>

</p>

<div class="mw-heading mw-heading2"><h2 id="Programming">Programming</h2></div>

<div role="note" class="hatnote navigation-not-searchable">Further information: <a href="Logic_synthesis" title="Logic synthesis">Logic synthesis</a>, <a href="Verification_and_validation" title="Verification and validation">Verification and validation</a>, and <a href="Place_and_route" title="Place and route">Place and route</a></div>

<p>To define the behavior of the FPGA, the user provides a design in a <a href="Hardware_description_language" title="Hardware description language">hardware description language</a> (HDL) or as a <a href="Schematic" title="Schematic">schematic</a> design. The HDL form is more suited to work with large structures because it's possible to specify high-level functional behavior rather than drawing every piece by hand. However, schematic entry can allow for easier visualization of a design and its <a href="Modular_programming" title="Modular programming">component modules</a>.

</p><p>Using an <a href="Electronic_design_automation" title="Electronic design automation">electronic design automation</a> tool, a technology-mapped <a href="Netlist" title="Netlist">netlist</a> is generated. The netlist can then be fit to the actual FPGA architecture using a process called <i><a href="Place_and_route" title="Place and route">place and route</a></i>, usually performed by the FPGA company's proprietary place-and-route software. The user will validate the results using <a href="Static_timing_analysis" title="Static timing analysis">timing analysis</a>, <a href="Simulation" title="Simulation">simulation</a>, and other <a href="Verification_and_validation" title="Verification and validation">verification and validation</a> techniques. Once the design and validation process is complete, the binary file generated, typically using the FPGA vendor's proprietary software, is used to (re-)configure the FPGA. This file is transferred to the FPGA via a <a href="Serial_communication" title="Serial communication">serial interface</a> (<a href="JTAG" title="JTAG">JTAG</a>) or to an external memory device such as an <a href="EEPROM" title="EEPROM">EEPROM</a>.

</p><p>The most common HDLs are <a href="VHDL" title="VHDL">VHDL</a> and <a href="Verilog" title="Verilog">Verilog</a>. <a href="National_Instruments" title="National Instruments">National Instruments</a>' <a href="LabVIEW" title="LabVIEW">LabVIEW</a> graphical programming language (sometimes referred to as <i>G</i>) has an FPGA add-in module available to target and program FPGA hardware. Verilog was created to simplify the process making HDL more robust and flexible. Verilog has a C-like syntax, unlike VHDL.<sup id="cite_ref-35" class="reference"><a href="#cite_note-35"><span class="cite-bracket">[</span>35<span class="cite-bracket">]</span></a></sup>

</p><p>To simplify the design of complex systems in FPGAs, there exist libraries of predefined complex functions and circuits that have been tested and optimized to speed up the design process. These predefined circuits are commonly called <i><a href="Semiconductor_intellectual_property_core" title="Semiconductor intellectual property core">intellectual property (IP) cores</a></i>, and are available from FPGA vendors and third-party IP suppliers. They are rarely free, and typically released under proprietary licenses. Other predefined circuits are available from developer communities such as <a href="OpenCores" title="OpenCores">OpenCores</a> (typically released under <a href="Free_and_open_source" class="mw-redirect" title="Free and open source">free and open source</a> licenses such as the <a href="GPL" class="mw-redirect" title="GPL">GPL</a>, <a href="BSD_license" class="mw-redirect" title="BSD license">BSD</a> or similar license). Such designs are known as <a href="Open-source_hardware" title="Open-source hardware">open-source hardware</a>.

</p><p>In a typical <a href="Design_flow" class="mw-redirect" title="Design flow">design flow</a>, an FPGA application developer will simulate the design at multiple stages throughout the design process. Initially the <a href="Register-transfer_level" title="Register-transfer level">RTL</a> description in <a href="VHDL" title="VHDL">VHDL</a> or <a href="Verilog" title="Verilog">Verilog</a> is simulated by creating <a href="Test_bench" title="Test bench">test benches</a> to simulate the system and observe results. Then, after the <a href="Logic_synthesis" title="Logic synthesis">synthesis</a> engine has mapped the design to a netlist, the netlist is translated to a <a href="Logic_gate" title="Logic gate">gate-level</a> description where simulation is repeated to confirm the synthesis proceeded without errors. Finally, the design is laid out in the FPGA at which point <a href="Propagation_delay" title="Propagation delay">propagation delay</a> values can be <a href="Back_annotation" class="mw-redirect" title="Back annotation">back-annotated</a> onto the netlist, and the simulation can be run again with these values.

</p><p>More recently, <a href="OpenCL" title="OpenCL">OpenCL</a> (Open Computing Language) is being used by programmers to take advantage of the performance and power efficiencies that FPGAs provide. OpenCL allows programmers to develop code in the <a href="C_programming_language" class="mw-redirect" title="C programming language">C programming language</a>.<sup id="cite_ref-36" class="reference"><a href="#cite_note-36"><span class="cite-bracket">[</span>36<span class="cite-bracket">]</span></a></sup> For further information, see <a href="High-level_synthesis" title="High-level synthesis">high-level synthesis</a> and <a href="C_to_HDL" title="C to HDL">C to HDL</a>.

</p><p>Most FPGAs rely on an <a href="Static_random-access_memory" title="Static random-access memory">SRAM</a>-based approach to be programmed. These FPGAs are in-system programmable and re-programmable, but require external boot devices. For example, <a href="Flash_memory" title="Flash memory">flash memory</a> or <a href="EEPROM" title="EEPROM">EEPROM</a> devices may load contents into internal SRAM that controls routing and logic. The SRAM approach is based on <a href="CMOS" title="CMOS">CMOS</a>.

</p><p>Rarer alternatives to the SRAM approach include:

</p>

<ul><li><a href="Fuse_(electrical)" title="Fuse (electrical)">Fuse</a>: one-time programmable. Bipolar. Obsolete.</li>

<li><a href="Antifuse" title="Antifuse">Antifuse</a>: one-time programmable. CMOS. Examples: Actel SX and Axcelerator families; Quicklogic Eclipse II family.<sup id="cite_ref-EDN_37-0" class="reference"><a href="#cite_note-EDN-37"><span class="cite-bracket">[</span>37<span class="cite-bracket">]</span></a></sup></li>

<li><a href="Programmable_read-only_memory" class="mw-redirect" title="Programmable read-only memory">PROM</a>: programmable read-only memory technology. One-time programmable because of plastic packaging. Obsolete.</li>

<li><a href="EPROM" title="EPROM">EPROM</a>: erasable programmable read-only memory technology. One-time programmable but with window, can be erased with ultraviolet (UV) light. CMOS. Obsolete.</li>

<li><a href="EEPROM" title="EEPROM">EEPROM</a>: electrically erasable programmable read-only memory technology. Can be erased, even in plastic packages. Some but not all EEPROM devices can be in-system programmed. CMOS.</li>

<li><a href="Flash_memory" title="Flash memory">Flash</a>: flash-erase EPROM technology. Can be erased, even in plastic packages. Some but not all flash devices can be in-system programmed. Usually, a flash cell is smaller than an equivalent EEPROM cell and is, therefore, less expensive to manufacture. CMOS. Example: Actel ProASIC family.<sup id="cite_ref-EDN_37-1" class="reference"><a href="#cite_note-EDN-37"><span class="cite-bracket">[</span>37<span class="cite-bracket">]</span></a></sup></li></ul>

<div class="mw-heading mw-heading2"><h2 id="Manufacturers">Manufacturers</h2></div>

<p>In 2016, long-time industry rivals <a href="Xilinx" title="Xilinx">Xilinx</a> (now part of <a href="AMD" title="AMD">AMD</a>) and <a href="Altera" title="Altera">Altera</a> (now part of <a href="Intel" title="Intel">Intel</a>) were the FPGA market leaders.<sup id="cite_ref-38" class="reference"><a href="#cite_note-38"><span class="cite-bracket">[</span>38<span class="cite-bracket">]</span></a></sup> At that time, they controlled nearly 90 percent of the market.

</p><p>Both Xilinx and Altera provide <a href="Proprietary_software" title="Proprietary software">proprietary</a> <a href="Electronic_design_automation" title="Electronic design automation">electronic design automation</a> software for <a href="Windows" class="mw-redirect" title="Windows">Windows</a> and <a href="Linux" title="Linux">Linux</a> (<a href="Xilinx_ISE" title="Xilinx ISE">ISE</a>/<a href="Vivado" title="Vivado">Vivado</a> and <a href="Intel_Quartus_Prime" class="mw-redirect" title="Intel Quartus Prime">Quartus</a>) which enables engineers to <a href="Hardware_design" class="mw-redirect" title="Hardware design">design</a>, analyze, <a href="Simulate" class="mw-redirect" title="Simulate">simulate</a>, and <a href="Logic_synthesis" title="Logic synthesis">synthesize</a> (<a href="Compile" class="mw-redirect" title="Compile">compile</a>) their designs.<sup id="cite_ref-39" class="reference"><a href="#cite_note-39"><span class="cite-bracket">[</span>39<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-40" class="reference"><a href="#cite_note-40"><span class="cite-bracket">[</span>40<span class="cite-bracket">]</span></a></sup>

</p><p>In March 2010, <a href="Tabula_(company)" class="mw-redirect" title="Tabula (company)">Tabula</a> announced their FPGA technology that uses <a href="Time-division_multiplexing" title="Time-division multiplexing">time-multiplexed</a> logic and interconnect that claims potential cost savings for high-density applications.<sup id="cite_ref-41" class="reference"><a href="#cite_note-41"><span class="cite-bracket">[</span>41<span class="cite-bracket">]</span></a></sup> On March 24, 2015, Tabula officially shut down.<sup id="cite_ref-42" class="reference"><a href="#cite_note-42"><span class="cite-bracket">[</span>42<span class="cite-bracket">]</span></a></sup>

</p><p>On June 1, 2015, Intel announced it would acquire Altera for approximately <a href="US%24" class="mw-redirect" title="US$">US$</a>16.7 billion and completed the acquisition on December 30, 2015.<sup id="cite_ref-43" class="reference"><a href="#cite_note-43"><span class="cite-bracket">[</span>43<span class="cite-bracket">]</span></a></sup>

</p><p>On October 27, 2020, AMD announced it would acquire Xilinx<sup id="cite_ref-44" class="reference"><a href="#cite_note-44"><span class="cite-bracket">[</span>44<span class="cite-bracket">]</span></a></sup> and completed the acquisition valued at about US$50 billion in February 2022.<sup id="cite_ref-45" class="reference"><a href="#cite_note-45"><span class="cite-bracket">[</span>45<span class="cite-bracket">]</span></a></sup>

</p><p>In February 2024 Altera became independent of Intel again.<sup id="cite_ref-Intel_Launches_Altera_46-0" class="reference"><a href="#cite_note-Intel_Launches_Altera-46"><span class="cite-bracket">[</span>46<span class="cite-bracket">]</span></a></sup>

</p><p>Other manufacturers include:

</p>

<ul><li><a href="Achronix" title="Achronix">Achronix</a>, manufacturing SRAM based FPGAs with 1.5 GHz fabric speed<sup id="cite_ref-47" class="reference"><a href="#cite_note-47"><span class="cite-bracket">[</span>47<span class="cite-bracket">]</span></a></sup></li>

<li><a href="Altium" title="Altium">Altium</a>, provides system-on-FPGA hardware-software design environment.<sup id="cite_ref-48" class="reference"><a href="#cite_note-48"><span class="cite-bracket">[</span>48<span class="cite-bracket">]</span></a></sup></li>

<li>Cologne Chip, German government-backed designer and producer of FPGAs<sup id="cite_ref-49" class="reference"><a href="#cite_note-49"><span class="cite-bracket">[</span>49<span class="cite-bracket">]</span></a></sup></li>

<li>Efinix offers small to medium-sized FPGAs. They combine logic and routing interconnects into a configurable XLR cell.</li>

<li>GOWIN Semiconductors, manufacturing small and medium-sized SRAM and flash-based FPGAs. They also offer pin-compatible replacements for a few Xilinx, Altera and Lattice products.</li>

<li><a href="Lattice_Semiconductor" title="Lattice Semiconductor">Lattice Semiconductor</a> manufactures <a href="Low-power_electronics" title="Low-power electronics">low-power</a> SRAM-based FPGAs featuring integrated configuration flash, <a href="Instant-on" title="Instant-on">instant-on</a> and live <a href="Reconfigurable_computing" title="Reconfigurable computing">reconfiguration</a>

<ul><li><a href="SiliconBlue_Technologies" class="mw-redirect" title="SiliconBlue Technologies">SiliconBlue Technologies</a> provides extremely low-power SRAM-based FPGAs with optional integrated <a href="Non-volatile_memory" title="Non-volatile memory">nonvolatile</a> configuration memory; acquired by Lattice in 2011</li></ul></li>

<li><a href="Microchip_Technology" title="Microchip Technology">Microchip</a>:

<ul><li><a href="Microsemi" title="Microsemi">Microsemi</a> (previously <a href="Actel" title="Actel">Actel</a>), producing <a href="Antifuse" title="Antifuse">antifuse</a>, flash-based, <a href="Mixed-signal" class="mw-redirect" title="Mixed-signal">mixed-signal</a> FPGAs; acquired by Microchip in 2018</li>

<li><a href="Atmel" title="Atmel">Atmel</a>, a second source of some Altera-compatible devices; also FPSLIC mentioned above;<sup id="cite_ref-50" class="reference"><a href="#cite_note-50"><span class="cite-bracket">[</span>50<span class="cite-bracket">]</span></a></sup> acquired by Microchip in 2016</li></ul></li>

<li>QuickLogic manufactures ultra-low-power sensor hubs, extremely-low-powered, low-density SRAM-based FPGAs, with display bridges MIPI and RGB inputs; MIPI, RGB and LVDS outputs.<sup id="cite_ref-51" class="reference"><a href="#cite_note-51"><span class="cite-bracket">[</span>51<span class="cite-bracket">]</span></a></sup></li></ul>

<div class="mw-heading mw-heading2"><h2 id="Applications">Applications</h2></div>

<div role="note" class="hatnote navigation-not-searchable">See also: <a href="Hardware_acceleration" title="Hardware acceleration">Hardware acceleration</a></div>

<p>An FPGA can be used to solve any problem which is <a href="Computable" class="mw-redirect" title="Computable">computable</a>. FPGAs can be used to implement a <a href="Soft_microprocessor" title="Soft microprocessor">soft microprocessor</a>, such as the Xilinx <a href="MicroBlaze" title="MicroBlaze">MicroBlaze</a> or Altera <a href="Nios_II" title="Nios II">Nios II</a>. But their advantage lies in that they are significantly faster for some applications because of their <a href="Parallel_computing" title="Parallel computing">parallel nature</a> and <a href="Logic_optimization" title="Logic optimization">optimality</a> in terms of the number of gates used for certain processes.<sup id="cite_ref-Xilinx-Inc-Apr-2006-8-K_52-0" class="reference"><a href="#cite_note-Xilinx-Inc-Apr-2006-8-K-52"><span class="cite-bracket">[</span>52<span class="cite-bracket">]</span></a></sup>

</p><p>FPGAs were originally introduced as competitors to <a href="Complex_programmable_logic_device" title="Complex programmable logic device">CPLDs</a> to implement <a href="Glue_logic" title="Glue logic">glue logic</a> for <a href="Printed_circuit_board" title="Printed circuit board">printed circuit boards</a>. As their size, capabilities, and speed increased, FPGAs took over additional functions to the point where some are now marketed as full <a href="Systems_on_chip" class="mw-redirect" title="Systems on chip">systems on chips</a> (SoCs). Particularly with the introduction of dedicated <a href="Binary_multiplier" title="Binary multiplier">multipliers</a> into FPGA architectures in the late 1990s, applications that had traditionally been the sole reserve of <a href="Digital_signal_processor" title="Digital signal processor">digital signal processors</a> (DSPs) began to use FPGAs instead.<sup id="cite_ref-53" class="reference"><a href="#cite_note-53"><span class="cite-bracket">[</span>53<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-54" class="reference"><a href="#cite_note-54"><span class="cite-bracket">[</span>54<span class="cite-bracket">]</span></a></sup>

</p><p>The evolution of FPGAs has motivated an increase in the use of these devices, whose architecture allows the development of hardware solutions optimized for complex tasks, such as 3D MRI image segmentation, 3D discrete wavelet transform, tomographic image reconstruction, or PET/MRI systems.<sup id="cite_ref-55" class="reference"><a href="#cite_note-55"><span class="cite-bracket">[</span>55<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-56" class="reference"><a href="#cite_note-56"><span class="cite-bracket">[</span>56<span class="cite-bracket">]</span></a></sup> The developed solutions can perform intensive computation tasks with parallel processing, are dynamically reprogrammable, and have a low cost, all while meeting the hard real-time requirements associated with medical imaging.

</p><p>Another trend in the use of FPGAs is <a href="Hardware_acceleration" title="Hardware acceleration">hardware acceleration</a>, where one can use the FPGA to accelerate certain parts of an algorithm and share part of the computation between the FPGA and a general-purpose processor. The search engine <a href="Bing_(search_engine)" class="mw-redirect" title="Bing (search engine)">Bing</a> is noted for adopting FPGA acceleration for its search algorithm in 2014.<sup id="cite_ref-BingFPGA_57-0" class="reference"><a href="#cite_note-BingFPGA-57"><span class="cite-bracket">[</span>57<span class="cite-bracket">]</span></a></sup> As of 2018, FPGAs are seeing increased use as <a href="AI_accelerator" class="mw-redirect" title="AI accelerator">AI accelerators</a> including Microsoft's Project Catapult<sup id="cite_ref-ProjCatapult_11-1" class="reference"><a href="#cite_note-ProjCatapult-11"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup> and for accelerating <a href="Artificial_neural_network" class="mw-redirect" title="Artificial neural network">artificial neural networks</a> for <a href="Machine_learning" title="Machine learning">machine learning</a> applications.

</p><p>Originally, FPGAs were reserved for specific <a href="Vertical_application" class="mw-redirect" title="Vertical application">vertical applications</a> where the volume of production is small. For these low-volume applications, the premium that companies pay in hardware cost per unit for a programmable chip is more affordable than the development resources spent on creating an ASIC. Often a custom-made chip would be cheaper if made in larger quantities, but FPGAs may be chosen to quickly bring a product to market. By 2017, new cost and performance dynamics broadened the range of viable applications.

</p><p>Other uses for FPGAs include:

</p>

<ul><li>Space (with <a href="Radiation_hardening" title="Radiation hardening">radiation hardening</a><sup id="cite_ref-58" class="reference"><a href="#cite_note-58"><span class="cite-bracket">[</span>58<span class="cite-bracket">]</span></a></sup>)</li>

<li><a href="Hardware_security_module" title="Hardware security module">Hardware security modules</a><sup id="cite_ref-auto_59-0" class="reference"><a href="#cite_note-auto-59"><span class="cite-bracket">[</span>59<span class="cite-bracket">]</span></a></sup></li>

<li>High-speed financial transactions<sup id="cite_ref-60" class="reference"><a href="#cite_note-60"><span class="cite-bracket">[</span>60<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-61" class="reference"><a href="#cite_note-61"><span class="cite-bracket">[</span>61<span class="cite-bracket">]</span></a></sup></li>

<li><a href="Retrocomputing" title="Retrocomputing">Retrocomputing</a> (e.g. the MARS and <a href="MiSTer" title="MiSTer">MiSTer</a> FPGA projects)<sup id="cite_ref-62" class="reference"><a href="#cite_note-62"><span class="cite-bracket">[</span>62<span class="cite-bracket">]</span></a></sup></li>

<li>Large scale integrated <a href="Digital_differential_analyzer" title="Digital differential analyzer">digital differential analyzers</a>, a form of an <a href="Analog_computer" title="Analog computer">analog computer</a> based on digital computing elements<sup id="cite_ref-63" class="reference"><a href="#cite_note-63"><span class="cite-bracket">[</span>63<span class="cite-bracket">]</span></a></sup></li></ul>

<div class="mw-heading mw-heading3"><h3 id="Usage_by_United_States_military">Usage by United States military</h3></div>

<p>FPGAs play a crucial role in modern military communications, especially in systems like the <a href="Joint_Tactical_Radio_System" title="Joint Tactical Radio System">Joint Tactical Radio System</a> (JTRS) and in devices from companies such as <a href="Thales_Group" title="Thales Group">Thales</a> and <a href="Harris_Corporation" title="Harris Corporation">Harris Corporation</a>. Their flexibility and programmability make them ideal for military communications, offering customizable and secure signal processing. In the JTRS, used by the US military, FPGAs provide adaptability and real-time processing, crucial for meeting various communication standards and encryption methods.<sup id="cite_ref-64" class="reference"><a href="#cite_note-64"><span class="cite-bracket">[</span>64<span class="cite-bracket">]</span></a></sup>

</p>

<div class="mw-heading mw-heading2"><h2 id="Security">Security</h2></div>

<p>Concerning <a href="Hardware_security" title="Hardware security">hardware security</a>, FPGAs have both advantages and disadvantages as compared to ASICs or secure microprocessors. FPGAs' flexibility makes malicious modifications during <a href="Semiconductor_device_fabrication" title="Semiconductor device fabrication">fabrication</a> a lower risk.<sup id="cite_ref-paper_65-0" class="reference"><a href="#cite_note-paper-65"><span class="cite-bracket">[</span>65<span class="cite-bracket">]</span></a></sup> Previously, for many FPGAs, the design <a href="Bitstream" title="Bitstream">bitstream</a> was exposed while the FPGA loads it from external memory, typically during powerup. All major FPGA vendors now offer a spectrum of security solutions to designers such as bitstream <a href="Encryption" title="Encryption">encryption</a> and <a href="Authentication" title="Authentication">authentication</a>. For example, <a href="Altera" title="Altera">Altera</a> and <a href="Xilinx" title="Xilinx">Xilinx</a> offer <a href="Advanced_Encryption_Standard" title="Advanced Encryption Standard">AES</a> encryption (up to 256-bit) for bitstreams stored in an external flash memory. <a href="Physical_unclonable_function" title="Physical unclonable function">Physical unclonable functions</a> (PUFs) are integrated circuits that have their own unique signatures and can be used to secure FPGAs while taking up very little hardware space.<sup id="cite_ref-66" class="reference"><a href="#cite_note-66"><span class="cite-bracket">[</span>66<span class="cite-bracket">]</span></a></sup>

</p><p>FPGAs that store their configuration internally in nonvolatile flash memory, such as <a href="Microsemi" title="Microsemi">Microsemi</a>'s ProAsic 3 or <a href="Lattice_Semiconductor" title="Lattice Semiconductor">Lattice</a>'s XP2 programmable devices, do not expose the bitstream and do not need <a href="Encryption" title="Encryption">encryption</a>. Customers wanting a higher guarantee of tamper resistance can use write-once, antifuse FPGAs from vendors such as <a href="Microsemi" title="Microsemi">Microsemi</a>.

</p><p>With its Stratix 10 FPGAs and SoCs, <a href="Altera" title="Altera">Altera</a> introduced a Secure Device Manager and <a href="Physical_unclonable_function" title="Physical unclonable function">physical unclonable functions</a> to provide high levels of protection against physical attacks.<sup id="cite_ref-67" class="reference"><a href="#cite_note-67"><span class="cite-bracket">[</span>67<span class="cite-bracket">]</span></a></sup>

</p><p>In 2012 researchers Sergei Skorobogatov and Christopher Woods demonstrated that some FPGAs can be vulnerable to hostile intent. They discovered a critical <a href="Backdoor_(computing)" title="Backdoor (computing)">backdoor vulnerability</a> had been manufactured in silicon as part of the Actel/Microsemi ProAsic 3 making it vulnerable on many levels such as reprogramming crypto and <a href="Access_key" title="Access key">access keys</a>, accessing unencrypted bitstream, modifying <a href="Low-level" class="mw-redirect" title="Low-level">low-level</a> silicon features, and extracting <a href="Computer_configuration" title="Computer configuration">configuration</a> data.<sup id="cite_ref-68" class="reference"><a href="#cite_note-68"><span class="cite-bracket">[</span>68<span class="cite-bracket">]</span></a></sup>

</p><p>In 2020 a critical vulnerability (named Starbleed) was discovered in all Xilinx 7 series FPGAs that rendered bitstream encryption useless. There is no workaround. Xilinx did not produce a hardware revision. Ultrascale and later devices, already on the market at the time, were not affected.

</p>

<div class="mw-heading mw-heading2"><h2 id="Similar_technologies">Similar technologies</h2></div>

<p>Historically, FPGAs have been slower, less energy efficient and generally achieved less functionality than their fixed ASIC counterparts. A study from 2006 showed that designs implemented on FPGAs need on average 40 times as much area, draw 12 times as much dynamic power, and run at one third the speed of corresponding ASIC implementations.<sup id="cite_ref-FPGA-ASIC-comparison_69-0" class="reference"><a href="#cite_note-FPGA-ASIC-comparison-69"><span class="cite-bracket">[</span>69<span class="cite-bracket">]</span></a></sup>

</p><p>Advantages of FPGAs include the ability to reprogram equipment in the field to fix <a href="Bug_(computer_programming)" class="mw-redirect" title="Bug (computer programming)">bugs</a> or make other improvements. Some FPGAs have the capability of <a href="Partial_re-configuration" class="mw-redirect" title="Partial re-configuration">partial re-configuration</a> that lets one portion of the device be re-programmed while other portions continue running.<sup id="cite_ref-70" class="reference"><a href="#cite_note-70"><span class="cite-bracket">[</span>70<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-71" class="reference"><a href="#cite_note-71"><span class="cite-bracket">[</span>71<span class="cite-bracket">]</span></a></sup> Other advantages may include shorter <a href="Time_to_market" title="Time to market">time to market</a> and lower <a href="Non-recurring_engineering" title="Non-recurring engineering">non-recurring engineering</a> costs. Vendors can also take a middle road via <a href="FPGA_prototyping" title="FPGA prototyping">FPGA prototyping</a>: developing their prototype hardware on FPGAs, but manufacturing their final version as an ASIC after the design has been committed. This is often also the case with new processor designs.<sup id="cite_ref-72" class="reference"><a href="#cite_note-72"><span class="cite-bracket">[</span>72<span class="cite-bracket">]</span></a></sup>

</p><p>The primary differences between <a href="Complex_programmable_logic_device" title="Complex programmable logic device">complex programmable logic devices</a> (CPLDs) and FPGAs are <a href="Computer_architecture" title="Computer architecture">architectural</a>. A CPLD has a comparatively restrictive structure consisting of one or more programmable <a href="Canonical_normal_form" title="Canonical normal form">sum-of-products</a> logic arrays feeding a relatively small number of clocked <a href="Register_(computing)" class="mw-redirect" title="Register (computing)">registers</a>. As a result, CPLDs are less flexible but have the advantage of more predictable <a href="Latency_(engineering)" title="Latency (engineering)">timing delays</a> and <span class="citation-needed-content" style="padding-left:0.1em; padding-right:0.1em; color:var(--color-subtle, #54595d); border:1px solid var(--border-color-subtle, #c8ccd1);">a higher logic-to-interconnect ratio.</span> FPGA architectures, on the other hand, are dominated by <a href="Communications_subsystem" class="mw-redirect" title="Communications subsystem">interconnect</a>. This makes them far more flexible (in terms of the range of designs that are practical for implementation on them) but also far more complex to design for, or at least requiring more complex <a href="Electronic_design_automation" title="Electronic design automation">electronic design automation</a> (EDA) software. In practice, the distinction between FPGAs and CPLDs is often one of size as FPGAs are usually much larger in terms of resources than CPLDs. Typically only FPGAs contain more complex <a href="Functional_unit" class="mw-redirect" title="Functional unit">embedded functions</a> such as <a href="Adder_(electronics)" title="Adder (electronics)">adders</a>, <a href="Binary_multiplier" title="Binary multiplier">multipliers</a>, <a href="Computer_memory" title="Computer memory">memory</a>, and <a href="SerDes" title="SerDes">serializer/deserializers</a>. Another common distinction is that CPLDs contain embedded <a href="Flash_memory" title="Flash memory">flash memory</a> to store their configuration while FPGAs usually require external <a href="Non-volatile_memory" title="Non-volatile memory">non-volatile memory</a> (but not always). When a design requires simple instant-on <a href="Glue_logic" title="Glue logic">(logic is already configured at power-up)</a> CPLDs are generally preferred. For most other applications FPGAs are generally preferred. Sometimes both CPLDs and FPGAs are used in a single system design. In those designs, CPLDs generally perform glue logic functions and are responsible for "<a href="Booting" title="Booting">booting</a>" the FPGA as well as controlling <a href="Reset_(computing)" title="Reset (computing)">reset</a> and boot sequence of the complete circuit board. Therefore, depending on the application it may be judicious to use both FPGAs and CPLDs in a single design.<sup id="cite_ref-73" class="reference"><a href="#cite_note-73"><span class="cite-bracket">[</span>73<span class="cite-bracket">]</span></a></sup>

</p>

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<ul><li><a href="FPGA_Mezzanine_Card" title="FPGA Mezzanine Card">FPGA Mezzanine Card</a></li>

<li><a href="CRUVI_FPGA_Card" class="mw-redirect" title="CRUVI FPGA Card">CRUVI FPGA Card</a> FPGA daughter card standard of Standardization Group for Embedded Technologies e.V. (SGET)</li>

<li><a href="List_of_HDL_simulators" title="List of HDL simulators">List of HDL simulators</a></li></ul>

<div class="mw-heading mw-heading2"><h2 id="References">References</h2></div>

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</ol></div>

<div class="mw-heading mw-heading2"><h2 id="Further_reading">Further reading</h2></div>

<ul><li><cite id="CITEREFSadrozinskiWu2010" class="citation book cs1">Sadrozinski, Hartmut F.-W.; Wu, Jinyuan (2010). <i>Applications of Field-Programmable Gate Arrays in Scientific Research</i>. Taylor & Francis. <a href="ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <bdi>978-1-4398-4133-4</bdi>.</cite></li>

<li><cite id="CITEREFWirth1995" class="citation book cs1">Wirth, Niklaus (1995). <i>Digital Circuit Design An Introduction Textbook</i>. Springer. <a href="ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <bdi>978-3-540-58577-0</bdi>.</cite></li>

<li><cite id="CITEREFMitra2018" class="citation journal cs1">Mitra, Jubin (2018). <a rel="nofollow" class="external text" href="https://doi.org/10.1109%2FTVLSI.2017.2758807">"An FPGA-Based Phase Measurement System"</a>. <i>IEEE Transactions on Very Large Scale Integration (VLSI) Systems</i>. <b>26</b>. IEEE: <span class="nowrap">133–</span>142. <a href="Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<span class="id-lock-free" title="Freely accessible"><a rel="nofollow" class="external text" href="https://doi.org/10.1109%2FTVLSI.2017.2758807">10.1109/TVLSI.2017.2758807</a></span>. <a href="S2CID_(identifier)" class="mw-redirect" title="S2CID (identifier)">S2CID</a> <a rel="nofollow" class="external text" href="https://api.semanticscholar.org/CorpusID:4920719">4920719</a>.</cite></li>

<li>Mencer, Oskar et al. (2020). "The history, status, and future of FPGAs". Communications of the ACM. ACM. Vol. 63, No. 10. <a href="https://doi.org/10.1145/3410669" class="extiw external" title="doi:10.1145/3410669">doi:10.1145/3410669</a></li></ul>

<div class="mw-heading mw-heading2"><h2 id="External_links">External links</h2></div>

<ul><li><a rel="nofollow" class="external text" href="https://www.youtube.com/watch?v=gUsHwi4M4xE"><span class="">What is an FPGA?</span></a> on <a href="YouTube_video_(identifier)" class="mw-redirect" title="YouTube video (identifier)">YouTube</a></li>

<li><a rel="nofollow" class="external text" href="https://www.ikalogic.com/2023/02/18/migrating-from-mcu-to-fpga.html">Migrating from MCU to FPGA</a></li></ul>

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</style><div id="Electronic_components254" style="font-size:114%;margin:0 4em"><a href="Electronic_component" title="Electronic component">Electronic components</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;"><a href="Semiconductor_device" title="Semiconductor device">Semiconductor<br>devices</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="MOSFET" title="MOSFET">MOS <br>transistors</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Transistor" title="Transistor">Transistor</a></li>

<li><a href="BiCMOS" title="BiCMOS">BiCMOS</a></li>

<li><a href="Bio-FET" title="Bio-FET">BioFET</a></li>

<li><a href="Chemical_field-effect_transistor" title="Chemical field-effect transistor">Chemical field-effect transistor</a> (ChemFET)</li>

<li><a href="CMOS" title="CMOS">Complementary MOS</a> (CMOS)</li>

<li><a href="Depletion-load_NMOS_logic" title="Depletion-load NMOS logic">Depletion-load NMOS</a></li>

<li><a href="FinFET" class="mw-redirect" title="FinFET">Fin field-effect transistor</a> (FinFET)</li>

<li><a href="Floating-gate_MOSFET" title="Floating-gate MOSFET">Floating-gate MOSFET</a> (FGMOS)</li>

<li><a href="Insulated-gate_bipolar_transistor" title="Insulated-gate bipolar transistor">Insulated-gate bipolar transistor</a> (IGBT)</li>

<li><a href="ISFET" title="ISFET">ISFET</a></li>

<li><a href="LDMOS" title="LDMOS">LDMOS</a></li>

<li><a href="MOSFET" title="MOSFET">MOS field-effect transistor</a> (MOSFET)</li>

<li><a href="Multigate_device" title="Multigate device">Multi-gate field-effect transistor</a> (MuGFET)</li>

<li><a href="Power_MOSFET" title="Power MOSFET">Power MOSFET</a></li>

<li><a href="Thin-film_transistor" title="Thin-film transistor">Thin-film transistor</a> (TFT)</li>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Transistor" title="Transistor">Other <br>transistors</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Bipolar_junction_transistor" title="Bipolar junction transistor">Bipolar junction transistor</a> (BJT)</li>

<li><a href="Darlington_transistor" title="Darlington transistor">Darlington transistor</a></li>

<li><a href="Diffused_junction_transistor" title="Diffused junction transistor">Diffused junction transistor</a></li>

<li><a href="Field-effect_transistor" title="Field-effect transistor">Field-effect transistor</a> (FET)

<ul><li><a href="JFET" title="JFET">Junction Gate FET (JFET)</a></li>

<li><a href="Organic_field-effect_transistor" title="Organic field-effect transistor">Organic FET (OFET)</a></li></ul></li>

<li><a href="Light-emitting_transistor" title="Light-emitting transistor">Light-emitting transistor</a> (LET)

<ul><li><a href="Organic_light-emitting_transistor" title="Organic light-emitting transistor">Organic LET (OLET)</a></li></ul></li>

<li><a href="Pentode_transistor" title="Pentode transistor">Pentode transistor</a></li>

<li><a href="Point-contact_transistor" title="Point-contact transistor">Point-contact transistor</a></li>

<li><a href="Programmable_unijunction_transistor" title="Programmable unijunction transistor">Programmable unijunction transistor</a> (PUT)</li>

<li><a href="Static_induction_transistor" title="Static induction transistor">Static induction transistor</a> (SIT)</li>

<li><a href="Tetrode_transistor" title="Tetrode transistor">Tetrode transistor</a></li>

<li><a href="Unijunction_transistor" title="Unijunction transistor">Unijunction transistor</a> (UJT)</li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Diode" title="Diode">Diodes</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Avalanche_diode" title="Avalanche diode">Avalanche diode</a></li>

<li><a href="Constant-current_diode" title="Constant-current diode">Constant-current diode</a> (CLD, CRD)</li>

<li><a href="Gunn_diode" title="Gunn diode">Gunn diode</a></li>

<li><a href="Laser_diode" title="Laser diode">Laser diode</a> (LD)</li>

<li><a href="Light-emitting_diode" title="Light-emitting diode">Light-emitting diode</a> (LED)</li>

<li><a href="OLED" title="OLED">Organic light-emitting diode</a> (OLED)</li>

<li><a href="Photodiode" title="Photodiode">Photodiode</a></li>

<li><a href="PIN_diode" title="PIN diode">PIN diode</a></li>

<li><a href="Schottky_diode" title="Schottky diode">Schottky diode</a></li>

<li><a href="Step_recovery_diode" title="Step recovery diode">Step recovery diode</a></li>

<li><a href="Zener_diode" title="Zener diode">Zener diode</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Other <br>devices</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Printed_electronics" title="Printed electronics">Printed electronics</a></li>

<li><a href="Printed_circuit_board" title="Printed circuit board">Printed circuit board</a></li>

<li><a href="Heterostructure_barrier_varactor" title="Heterostructure barrier varactor">Heterostructure barrier varactor</a></li>

<li><a href="Integrated_circuit" title="Integrated circuit">Integrated circuit</a> (IC)</li>

<li><a href="Hybrid_integrated_circuit" title="Hybrid integrated circuit">Hybrid integrated circuit</a></li>

<li><a href="Light_emitting_capacitor" class="mw-redirect" title="Light emitting capacitor">Light emitting capacitor</a> (LEC)</li>

<li><a href="Memistor" title="Memistor">Memistor</a></li>

<li><a href="Memristor" title="Memristor">Memristor</a></li>

<li><a href="Memtransistor" title="Memtransistor">Memtransistor</a></li>

<li><a href="Memory_cell_(computing)" title="Memory cell (computing)">Memory cell</a></li>

<li><a href="Metal-oxide_varistor" class="mw-redirect" title="Metal-oxide varistor">Metal-oxide varistor</a> (MOV)</li>

<li><a href="Mixed-signal_integrated_circuit" title="Mixed-signal integrated circuit">Mixed-signal integrated circuit</a></li>

<li><a href="MOS_integrated_circuit" class="mw-redirect" title="MOS integrated circuit">MOS integrated circuit</a> (MOS IC)</li>

<li><a href="Organic_semiconductor" title="Organic semiconductor">Organic semiconductor</a></li>

<li><a href="Photodetector" title="Photodetector">Photodetector</a></li>

<li><a href="Quantum_circuit" title="Quantum circuit">Quantum circuit</a></li>

<li><a href="Silicon_controlled_rectifier" title="Silicon controlled rectifier">Silicon controlled rectifier</a> (SCR)</li>

<li><a href="Solaristor" title="Solaristor">Solaristor</a></li>

<li><a href="Static_induction_thyristor" title="Static induction thyristor">Static induction thyristor</a> (SITh)</li>

<li><a href="Three-dimensional_integrated_circuit" title="Three-dimensional integrated circuit">Three-dimensional integrated circuit</a> (3D IC)</li>

<li><a href="Thyristor" title="Thyristor">Thyristor</a></li>

<li><a href="Trancitor" title="Trancitor">Trancitor</a></li>

<li><a href="TRIAC" title="TRIAC">TRIAC</a></li>

<li><a href="Varicap" title="Varicap">Varicap</a></li></ul>

</div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;"><a href="Voltage_regulator" title="Voltage regulator">Voltage regulators</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Linear_regulator" title="Linear regulator">Linear regulator</a></li>

<li><a href="Low-dropout_regulator" title="Low-dropout regulator">Low-dropout regulator</a></li>

<li><a href="Switching_regulator" class="mw-redirect" title="Switching regulator">Switching regulator</a></li>

<li><a href="Boost_converter" title="Boost converter">Boost</a></li>

<li><a href="Buck%E2%80%93boost_converter" title="Buck–boost converter">Buck–boost</a></li>

<li><a href="Split-pi_topology" title="Split-pi topology">Split-pi</a></li>

<li><a href="Single-ended_primary-inductor_converter" title="Single-ended primary-inductor converter">SEPIC</a></li>

<li><a href="Charge_pump" title="Charge pump">Charge pump</a></li>

<li><a href="Switched_capacitor" title="Switched capacitor">Switched capacitor</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;"><a href="Vacuum_tube" title="Vacuum tube">Vacuum tubes</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Acorn_tube" title="Acorn tube">Acorn tube</a></li>

<li><a href="Audion" title="Audion">Audion</a></li>

<li><a href="Beam_tetrode" title="Beam tetrode">Beam tetrode</a></li>

<li><a href="Hot-wire_barretter" title="Hot-wire barretter">Barretter</a></li>

<li><a href="Compactron" title="Compactron">Compactron</a></li>

<li><a href="Vacuum_diode" class="mw-redirect" title="Vacuum diode">Diode</a></li>

<li><a href="Fleming_valve" title="Fleming valve">Fleming valve</a></li>

<li><a href="Neutron_generator" title="Neutron generator">Neutron tube</a></li>

<li><a href="Nonode" title="Nonode">Nonode</a></li>

<li><a href="Nuvistor" title="Nuvistor">Nuvistor</a></li>

<li><a href="Pentagrid_converter" title="Pentagrid converter">Pentagrid</a> (Hexode, Heptode, Octode)</li>

<li><a href="Pentode" title="Pentode">Pentode</a></li>

<li><a href="Photomultiplier_tube" title="Photomultiplier tube">Photomultiplier</a></li>

<li><a href="Phototube" title="Phototube">Phototube</a></li>

<li><a href="Tetrode" title="Tetrode">Tetrode</a></li>

<li><a href="Triode" title="Triode">Triode</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;"><a href="Vacuum_tube" title="Vacuum tube">Vacuum tubes</a> (<a href="Electromagnetic_radiation" title="Electromagnetic radiation">RF</a>)</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Backward-wave_oscillator" title="Backward-wave oscillator">Backward-wave oscillator</a> (BWO)</li>

<li><a href="Cavity_magnetron" title="Cavity magnetron">Cavity magnetron</a></li>

<li><a href="Crossed-field_amplifier" title="Crossed-field amplifier">Crossed-field amplifier</a> (CFA)</li>

<li><a href="Gyrotron" title="Gyrotron">Gyrotron</a></li>

<li><a href="Inductive_output_tube" title="Inductive output tube">Inductive output tube</a> (IOT)</li>

<li><a href="Klystron" title="Klystron">Klystron</a></li>

<li><a href="Maser" title="Maser">Maser</a></li>

<li><a href="Sutton_tube" title="Sutton tube">Sutton tube</a></li>

<li><a href="Traveling-wave_tube" title="Traveling-wave tube">Traveling-wave tube</a> (TWT)</li>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;"><a href="Cathode-ray_tube" title="Cathode-ray tube">Cathode-ray tubes</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Beam_deflection_tube" title="Beam deflection tube">Beam deflection tube</a></li>

<li><a href="Charactron" title="Charactron">Charactron</a></li>

<li><a href="Iconoscope" title="Iconoscope">Iconoscope</a></li>

<li><a href="Magic_eye_tube" title="Magic eye tube">Magic eye tube</a></li>

<li><a href="Monoscope" title="Monoscope">Monoscope</a></li>

<li><a href="Selectron_tube" title="Selectron tube">Selectron tube</a></li>

<li><a href="Storage_tube" title="Storage tube">Storage tube</a></li>

<li><a href="Trochotron" class="mw-redirect" title="Trochotron">Trochotron</a></li>

<li><a href="Video_camera_tube" title="Video camera tube">Video camera tube</a></li>

<li><a href="Williams_tube" title="Williams tube">Williams tube</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;"><a href="Gas-filled_tube" title="Gas-filled tube">Gas-filled tubes</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Cold_cathode" title="Cold cathode">Cold cathode</a></li>

<li><a href="Crossatron" title="Crossatron">Crossatron</a></li>

<li><a href="Dekatron" title="Dekatron">Dekatron</a></li>

<li><a href="Ignitron" title="Ignitron">Ignitron</a></li>

<li><a href="Krytron" title="Krytron">Krytron</a></li>

<li><a href="Mercury-arc_valve" title="Mercury-arc valve">Mercury-arc valve</a></li>

<li><a href="Nixie_tube" title="Nixie tube">Nixie tube</a></li>

<li><a href="Thyratron" title="Thyratron">Thyratron</a></li>

<li><a href="Trigatron" title="Trigatron">Trigatron</a></li>

<li><a href="Voltage-regulator_tube" title="Voltage-regulator tube">Voltage-regulator tube</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;">Adjustable</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Potentiometer" title="Potentiometer">Potentiometer</a>

<ul><li><a href="Digital_potentiometer" title="Digital potentiometer">digital</a></li></ul></li>

<li><a href="Variable_capacitor" title="Variable capacitor">Variable capacitor</a></li>

<li><a href="Varicap" title="Varicap">Varicap</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;">Passive</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li>Connector

<ul><li><a href="Audio_and_video_interfaces_and_connectors" title="Audio and video interfaces and connectors">audio and video</a></li>

<li><a href="AC_power_plugs_and_sockets" title="AC power plugs and sockets">electrical power</a></li>

<li><a href="Electrolytic_detector" title="Electrolytic detector">Electrolytic detector</a></li>

<li><a href="Ferrite_core" title="Ferrite core">Ferrite</a></li>

<li><a href="Antifuse" title="Antifuse">Antifuse</a></li>

<ul><li><a href="Resettable_fuse" title="Resettable fuse">resettable</a></li>

<li><a href="EFUSE" class="mw-redirect" title="EFUSE">eFUSE</a></li></ul></li>

<li><a href="Resistor" title="Resistor">Resistor</a></li>

<li><a href="Switch" title="Switch">Switch</a></li>

<li><a href="Thermistor" title="Thermistor">Thermistor</a></li>

<li><a href="Transformer" title="Transformer">Transformer</a></li>

<li><a href="Varistor" title="Varistor">Varistor</a></li>

<ul><li><a href="Wollaston_wire" title="Wollaston wire">Wollaston wire</a></li></ul></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;"><a href="Electrical_reactance" title="Electrical reactance">Reactive</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Capacitor" title="Capacitor">Capacitor</a>

<ul><li><a href="Capacitor_types" title="Capacitor types">types</a></li></ul></li>

<li><a href="Ceramic_resonator" title="Ceramic resonator">Ceramic resonator</a></li>

<li><a href="Crystal_oscillator" title="Crystal oscillator">Crystal oscillator</a></li>

<li><a href="Inductor" title="Inductor">Inductor</a></li>

<li><a href="Parametron" title="Parametron">Parametron</a></li>

<li><a href="Relay" title="Relay">Relay</a>

<ul><li><a href="Reed_relay" title="Reed relay">reed relay</a></li>

<li><a href="Mercury_relay" title="Mercury relay">mercury relay</a></li></ul></li></ul>

</div></td></tr></tbody></table></div>

<div class="navbox-styles"></div><div role="navigation" class="navbox" aria-labelledby="Semiconductor_packages323" style="wide;padding:3px"><table class="nowraplinks mw-collapsible autocollapse navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><div id="Semiconductor_packages323" style="font-size:114%;margin:0 4em"><a href="Semiconductor_package" title="Semiconductor package">Semiconductor packages</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:left;">Single <a href="Diode" title="Diode">diode</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:left;"><a href="Semiconductor_device" title="Semiconductor device">3...5-pin</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<li><a href="TO-3" title="TO-3">TO-3</a> (TH / Panel)</li>

<li><a href="TO-66" title="TO-66">TO-66</a> (TH / Panel)</li>

<li><a href="TO-126" title="TO-126">TO-126</a> (TH / Panel)</li>

<li>TO-202 (TH / Panel)</li>

<li><a href="TO-220" title="TO-220">TO-220</a> (TH / Panel)</li>

<li>TO-247 (TH / Panel)</li>

<li>TO-273 (Super-220) (SMT)</li>

<li>TO-274 (Super-247) (SMT)</li>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:left;">Single row</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:left;">Dual row</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<li><a href="Thin_small_outline_package" title="Thin small outline package">TSOP / HTSOP</a></li>

<li><a href="Thin_shrink_small_outline_package" title="Thin shrink small outline package">TSSOP / HTSSOP</a></li>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:left;">Quad row</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:left;">Grid array</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:left;"><a href="Wafer_(electronics)" title="Wafer (electronics)">Wafer</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:left;">Related topics</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Electronic_packaging" title="Electronic packaging">Electronic packaging</a></li>

<li><a href="Integrated_circuit_packaging" title="Integrated circuit packaging">Integrated circuit packaging</a></li>

<li><a href="List_of_electronic_component_packaging_types" title="List of electronic component packaging types">List of electronic component packaging types</a></li>

<li><a href="Printed_circuit_board" title="Printed circuit board">Printed circuit board</a></li>

<li><a href="Surface-mount_technology" title="Surface-mount technology">Surface-mount technology</a></li>

<li><a href="Through-hole_technology" title="Through-hole technology">Through-hole technology</a></li></ul>

</div></td></tr><tr><td class="navbox-abovebelow" colspan="2"><div>It is relatively common to find packages that contain other components than their designated ones, such as diodes or <a href="Voltage_regulator" title="Voltage regulator">voltage regulators</a> in transistor packages, etc.</div></td></tr></tbody></table></div>

<div class="navbox-styles"></div><div role="navigation" class="navbox" aria-labelledby="Digital_electronics118" style="padding:3px"><table class="nowraplinks mw-collapsible autocollapse navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><div id="Digital_electronics118" style="font-size:114%;margin:0 4em"><a href="Digital_electronics" title="Digital electronics">Digital electronics</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;"><a href="Electronic_component" title="Electronic component">Components</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Transistor" title="Transistor">Transistor</a></li>

<li><a href="Resistor" title="Resistor">Resistor</a></li>

<li><a href="Inductor" title="Inductor">Inductor</a></li>

<li><a href="Capacitor" title="Capacitor">Capacitor</a></li>

<li><a href="Printed_electronics" title="Printed electronics">Printed electronics</a></li>

<li><a href="Printed_circuit_board" title="Printed circuit board">Printed circuit board</a></li>

<li><a href="Electronic_circuit" title="Electronic circuit">Electronic circuit</a></li>

<li><a href="Memory_cell_(computing)" title="Memory cell (computing)">Memory cell</a></li>

<li><a href="Combinational_logic" title="Combinational logic">Combinational logic</a></li>

<li><a href="Sequential_logic" title="Sequential logic">Sequential logic</a></li>

<li><a href="Logic_gate" title="Logic gate">Logic gate</a></li>

<li><a href="Boolean_circuit" title="Boolean circuit">Boolean circuit</a></li>

<li><a href="Integrated_circuit" title="Integrated circuit">Integrated circuit</a> (IC)</li>

<li><a href="Hybrid_integrated_circuit" title="Hybrid integrated circuit">Hybrid integrated circuit</a> (HIC)</li>

<li><a href="Mixed-signal_integrated_circuit" title="Mixed-signal integrated circuit">Mixed-signal integrated circuit</a></li>

<li><a href="Three-dimensional_integrated_circuit" title="Three-dimensional integrated circuit">Three-dimensional integrated circuit</a> (3D IC)</li>

<li><a href="Emitter-coupled_logic" title="Emitter-coupled logic">Emitter-coupled logic</a> (ECL)</li>

<li><a href="Erasable_programmable_logic_device" class="mw-redirect" title="Erasable programmable logic device">Erasable programmable logic device</a> (EPLD)</li>

<li><a href="Macrocell_array" title="Macrocell array">Macrocell array</a></li>

<li><a href="Programmable_logic_array" title="Programmable logic array">Programmable logic array</a> (PLA)</li>

<li><a href="Programmable_logic_device" title="Programmable logic device">Programmable logic device</a> (PLD)</li>

<li><a href="Programmable_Array_Logic" title="Programmable Array Logic">Programmable Array Logic</a> (PAL)</li>

<li><a href="Generic_Array_Logic" title="Generic Array Logic">Generic Array Logic</a> (GAL)</li>

<li><a href="Complex_programmable_logic_device" title="Complex programmable logic device">Complex programmable logic device</a> (CPLD)</li>

<li><a href="Field-programmable_object_array" title="Field-programmable object array">Field-programmable object array</a> (FPOA)</li>

<li><a href="Application-specific_integrated_circuit" title="Application-specific integrated circuit">Application-specific integrated circuit</a> (ASIC)</li>

<li><a href="Tensor_Processing_Unit" title="Tensor Processing Unit">Tensor Processing Unit</a> (TPU)</li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;">Theory</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Digital_signal" title="Digital signal">Digital signal</a></li>

<li><a href="Boolean_algebra" title="Boolean algebra">Boolean algebra</a></li>

<li><a href="Logic_synthesis" title="Logic synthesis">Logic synthesis</a></li>

<li><a href="Logic_in_computer_science" title="Logic in computer science">Logic in computer science</a></li>

<li><a href="Computer_architecture" title="Computer architecture">Computer architecture</a></li>

<li><a href="Digital_signal_(signal_processing)" title="Digital signal (signal processing)">Digital signal</a>

<ul><li><a href="Digital_signal_processing" title="Digital signal processing">Digital signal processing</a></li></ul></li>

<li><a href="Circuit_minimization_for_Boolean_functions" class="mw-redirect" title="Circuit minimization for Boolean functions">Circuit minimization</a></li>

<li><a href="Switching_circuit_theory" title="Switching circuit theory">Switching circuit theory</a></li>

<li><a href="Gate_equivalent" title="Gate equivalent">Gate equivalent</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;"><a href="Electronics_design" class="mw-redirect" title="Electronics design">Design</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Logic_synthesis" title="Logic synthesis">Logic synthesis</a></li>

<li><a href="Place_and_route" title="Place and route">Place and route</a>

<ul><li><a href="Placement_(electronic_design_automation)" title="Placement (electronic design automation)">Placement</a></li>

<li><a href="Routing_(electronic_design_automation)" title="Routing (electronic design automation)">Routing</a></li></ul></li>

<li><a href="Transaction-level_modeling" title="Transaction-level modeling">Transaction-level modeling</a></li>

<li><a href="Register-transfer_level" title="Register-transfer level">Register-transfer level</a>

<ul><li><a href="Hardware_description_language" title="Hardware description language">Hardware description language</a></li>

<li><a href="High-level_synthesis" title="High-level synthesis">High-level synthesis</a></li></ul></li>

<li><a href="Formal_equivalence_checking" title="Formal equivalence checking">Formal equivalence checking</a></li>

<li><a href="Synchronous_circuit" title="Synchronous circuit">Synchronous logic</a></li>

<li><a href="Asynchronous_circuit" title="Asynchronous circuit">Asynchronous logic</a></li>

<li><a href="Finite-state_machine" title="Finite-state machine">Finite-state machine</a>

<ul><li><a href="Hierarchical_state_machine" class="mw-redirect" title="Hierarchical state machine">Hierarchical state machine</a></li></ul></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;">Applications</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Computer_hardware" title="Computer hardware">Computer hardware</a>

<ul><li><a href="Hardware_acceleration" title="Hardware acceleration">Hardware acceleration</a></li></ul></li>

<li><a href="Digital_audio" title="Digital audio">Digital audio</a>

<ul><li><a href="Digital_radio" title="Digital radio">radio</a></li></ul></li>

<li><a href="Digital_photography" title="Digital photography">Digital photography</a></li>

<li><a href="Telephony#Digital_telephony" title="Telephony">Digital telephone</a></li>

<li><a href="Digital_video" title="Digital video">Digital video</a>

<ul><li><a href="Digital_cinematography" title="Digital cinematography">cinematography</a></li>

<li><a href="Digital_television" title="Digital television">television</a></li></ul></li>

<li><a href="Electronic_literature" title="Electronic literature">Electronic literature</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;">Design issues</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Metastability_(electronics)" title="Metastability (electronics)">Metastability</a></li>

<li><a href="Runt_pulse" title="Runt pulse">Runt pulse</a></li></ul>

</div></td></tr></tbody></table></div>

<div class="navbox-styles"></div><div role="navigation" class="navbox" aria-labelledby="Programmable_logic116" style="padding:3px"><table class="nowraplinks mw-collapsible autocollapse navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><div id="Programmable_logic116" style="font-size:114%;margin:0 4em"><a href="Programmable_logic_device" title="Programmable logic device">Programmable logic</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%">Concepts</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<li>

<ul><li><a href="Logic_block" title="Logic block">Logic block</a></li></ul></li>

<li><a href="Reconfigurable_computing" title="Reconfigurable computing">Reconfigurable computing</a>

<ul><li><a href="Xputer" title="Xputer">Xputer</a></li></ul></li>

<li><a href="Soft_microprocessor" title="Soft microprocessor">Soft microprocessor</a></li>

<li><a href="Circuit_underutilization" title="Circuit underutilization">Circuit underutilization</a></li>

<li><a href="High-level_synthesis" title="High-level synthesis">High-level synthesis</a></li>

<li><a href="Hardware_acceleration" title="Hardware acceleration">Hardware acceleration</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Hardware_description_language" title="Hardware description language">Languages</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Verilog" title="Verilog">Verilog</a>

<li><a href="VHDL-VITAL" class="mw-redirect" title="VHDL-VITAL">VITAL</a></li></ul></li>

<li><a href="SystemVerilog" title="SystemVerilog">SystemVerilog</a>

<li><a href="SystemC" title="SystemC">SystemC</a></li>

<li><a href="Handel-C" title="Handel-C">Handel-C</a></li>

<li><a href="PALASM" title="PALASM">PALASM</a></li>

<li><a href="MyHDL" title="MyHDL">MyHDL</a></li>

<li><a href="Chisel_(programming_language)" title="Chisel (programming language)">Chisel</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Companies</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Accellera" title="Accellera">Accellera</a></li>

<li><a href="Achronix" title="Achronix">Achronix</a></li>

<li><a href="Aldec" title="Aldec">Aldec</a></li>

<li><a href="Cadence_Design_Systems" title="Cadence Design Systems">Cadence</a></li>

<li><a href="Infineon_Technologies" title="Infineon Technologies">Infineon</a></li>

<li><a href="Intel" title="Intel">Intel</a></li>

<li><a href="Lattice_Semiconductor" title="Lattice Semiconductor">Lattice</a></li>

<li><a href="Microchip_Technology" title="Microchip Technology">Microchip Technology</a></li>

<li><a href="Siemens" title="Siemens">Siemens</a></li>

<li><a href="Synopsys" title="Synopsys">Synopsys</a></li>

<li><a href="Texas_Instruments" title="Texas Instruments">Texas Instruments</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Products</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Hardware</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<li><a href="Stratix" title="Stratix">Stratix</a></li>

<li><a href="Virtex_(FPGA)" title="Virtex (FPGA)">Virtex</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Software</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Intel_Quartus_Prime" class="mw-redirect" title="Intel Quartus Prime">Intel Quartus Prime</a></li>

<li><a href="Xilinx_ISE" title="Xilinx ISE">Xilinx ISE</a></li>

<li><a href="Vivado" title="Vivado">Vivado</a></li>

<li><a href="ModelSim" title="ModelSim">ModelSim</a></li>

<li><a href="List_of_HDL_simulators" title="List of HDL simulators">Simulators</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Intellectual_property" title="Intellectual property">Intellectual<br>property</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Proprietary_hardware" title="Proprietary hardware">Proprietary</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<li><a href="ARM_Cortex-M" title="ARM Cortex-M">ARM Cortex-M</a></li>

<li><a href="LatticeMico8" title="LatticeMico8">LatticeMico8</a></li>

<li><a href="MicroBlaze" title="MicroBlaze">MicroBlaze</a></li>

<li><a href="PicoBlaze" title="PicoBlaze">PicoBlaze</a></li>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Open-source_hardware" title="Open-source hardware">Open-source</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<li><a href="LatticeMico32" title="LatticeMico32">LatticeMico32</a></li>

<li><a href="OpenCores" title="OpenCores">OpenCores</a></li>

<li><a href="OpenRISC" title="OpenRISC">OpenRISC</a>

<li><a href="Power_ISA" title="Power ISA">Power ISA</a>

<ul><li><a href="Libre-SOC" title="Libre-SOC">Libre-SOC</a></li>

<li><a href="OpenPOWER_Microwatt" title="OpenPOWER Microwatt">Microwatt</a></li></ul></li>

</div></td></tr></tbody></table><div></div></td></tr></tbody></table><div></div></td></tr></tbody></table></div>

<div class="navbox-styles"></div><div role="navigation" class="navbox" aria-labelledby="Hardware_acceleration129" style="padding:3px"><table class="nowraplinks mw-collapsible autocollapse navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><div id="Hardware_acceleration129" style="font-size:114%;margin:0 4em"><a href="Hardware_acceleration" title="Hardware acceleration">Hardware acceleration</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Model_of_computation" title="Model of computation">Theory</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Universal_Turing_machine" title="Universal Turing machine">Universal Turing machine</a></li>

<li><a href="Parallel_computing" title="Parallel computing">Parallel computing</a></li>

<li><a href="Distributed_computing" title="Distributed computing">Distributed computing</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Applications</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="General-purpose_computing_on_graphics_processing_units" title="General-purpose computing on graphics processing units">GPGPU</a></li>

<li><a href="DirectX_Video_Acceleration" title="DirectX Video Acceleration">DirectX</a></li></ul></li>

<li><a href="Sound_card" title="Sound card">Audio</a></li>

<li><a href="Digital_signal_processor" title="Digital signal processor">Digital signal processing</a></li>

<li><a href="Hardware_random_number_generator" title="Hardware random number generator">Hardware random number generation</a></li>

<li><a href="Neural_processing_unit" title="Neural processing unit">Neural processing unit</a></li>

<li><a href="Cryptographic_accelerator" title="Cryptographic accelerator">Cryptography</a>

<li><a href="Vision_processing_unit" title="Vision processing unit">Machine vision</a></li>

<li><a href="Custom_hardware_attack" title="Custom hardware attack">Custom hardware attack</a>

<ul><li><a href="Scrypt" title="Scrypt">scrypt</a></li></ul></li>

<li><a href="Network_processor" title="Network processor">Networking</a></li>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Implementations</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="High-level_synthesis" title="High-level synthesis">High-level synthesis</a>

<li><a href="System_on_a_chip" title="System on a chip">System on a chip</a>

<ul><li><a href="Network_on_a_chip" title="Network on a chip">Network on a chip</a></li></ul></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Computer_architecture" title="Computer architecture">Architectures</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Dataflow_architecture" title="Dataflow architecture">Dataflow</a></li>

<li><a href="Transport_triggered_architecture" title="Transport triggered architecture">Transport triggered</a></li>

<li><a href="Multi-core_processor" title="Multi-core processor">Multicore</a></li>

<li><a href="Manycore_processor" title="Manycore processor">Manycore</a></li>

<li><a href="Heterogeneous_computing" title="Heterogeneous computing">Heterogeneous</a></li>

<li><a href="In-memory_processing" title="In-memory processing">In-memory computing</a></li>

<li><a href="Systolic_array" title="Systolic array">Systolic array</a></li>

<li><a href="Neuromorphic_computing" title="Neuromorphic computing">Neuromorphic</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Related</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Programmable_logic_device" title="Programmable logic device">Programmable logic</a></li>

<li><a href="Processor_(computing)" title="Processor (computing)">Processor</a>

<ul><li><a href="Processor_design" title="Processor design">design</a></li>

<li><a href="Microprocessor_chronology" title="Microprocessor chronology">chronology</a></li></ul></li>

<li><a href="Digital_electronics" title="Digital electronics">Digital electronics</a></li>

<li><a href="Virtualization" title="Virtualization">Virtualization</a>

<ul><li><a href="Hardware_emulation" title="Hardware emulation">Hardware emulation</a></li></ul></li>

<li><a href="Logic_synthesis" title="Logic synthesis">Logic synthesis</a></li>

<li><a href="Embedded_system" title="Embedded system">Embedded systems</a></li></ul>

</div></td></tr></tbody></table></div>

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